Over the last 50 years the CMOS scaling has allowed manufacturing of Integrated Circuits (ICs) with predictable increase in
efficiency. The major barrier that CMOS technology is facing today are the physical limits of sub-10nm processes, which are preventing
further cost-effective down-scaling of ICs. The only alternative to still continue to increase the IC performance (i.e.
cost-effective enablement of advanced IC processes) is to dramatically increase the number ICs deployed, with identical layout.

Conversely, the rise of new computing paradigms such as Internet-of-Things (IoT) and Internet-of- Everything (IoE) (billions of
devices foreseen in 2020) requires extremely versatile IC solutions. To support this wide variety of applications, including the
existing mobile and high-performance comput- ing, extremely configurable systems – both at design-time and run-time – will be
required.

The SOFIST project aims at designing highly scalable, low-cost, template System-on-Chip (SoC) archi- tectures for CLOUD-OF-CHIPS
applications. CLOUD-OF-CHIPS refers to large amounts of interconnected ICs and IC cores (which may or may not be on the same
board), which can have different communi- cation speeds and hierarchy levels. The proposed architecture is configurable: 1) at
design-time (core template architecture, size of tightly coupled computing clusters, etc.), and 2) at run-time (depending on the
application: IC communication scheme, security features, size of computing clusters, etc.).